Digital phase comparator capable of in dicating greater than 360 degree phase differences



c. E. LENz 3,329,895 DIGITAL PHASE COMPARATOR CAPABLE OF INDICATING July 4, 1967 GREATER THAN 560 DEGREE PHASE DIFFERENCES 8 Sheets-Sheet 1 Filed July 2, 1964 I] VEN TOR.

LENZ

CHARLES ATTORNEY c. E. LENz 3,329,895 DIGITAL PHASE COMPARATOR CAPABLE OF INDICATNG July4. 1967 GREATER THAN 360 DEGREE PHASE DIFFERENCES 8 Sheets-Sheet 2 Filed July 2, 1964 50.5 I 52.5 EN @E INVENTOR. CHARLES E. Ll-:Nz

BY 7 Q/ ATTORNEY July 4. 1967 C. E. L ENZ 3,329,895

DIGITAL PHASE COMPARATOR CAPABLE OF INDICATING GREATER THAN 560 DEGREE PHASE DIPFERENCES Filed July 2, 1964 8 Sheets-Sheet 5 l H614@ I o I I I I I I I I e l FIGAm C2 o I I I I I I I I Premi) FlaA FGHC) 6| 0^ FIGA@ T" qxl I FIGAm) e0 o 1 FIG. 4(k)` FIGAH) X= 6,5

1N VENTOR CHARLES E. LENZ :Hwy/@7 I ATTORNEY C. E. LENZ DIGITAL PHASE COMPARATOR CAPABLE OF INDICATING `uly 4, 1967 GREATER THAN 360 DEGREE PHASE DIFFERENCES 8 Sheets-Sheet 4 Filed July 2, 1964 El.lilllilil Il .i

v EON-m INVENTOR. CHARLES E. LENZ M2M y@ ATTORNEYVv July 4. 1967 c. E. I ,ENz 3,329,895

DIGITAL PHASE COMPARATOR CAPABLE OF' INDICATING GREATER THAN 360 DEGREE PHASE DIFFERENCES Filed July 2, 1964 8 Sheets-Sheet 5 INVENTOR. CHARLES E LENZ BWM/? ATTO NEY July 4, 1967 c. E. LENz 3,329,895

DIGITAL PHASE COMPARATGR GAPAEEE GE INDIGATING GREATER THAN :5Go DEGREE PHASE DTEEERENCES Filed July E, 1964 8 Sheets-Sheet 6 STEP COUNT VOLTS CHARLES E LENZ YATTORNEY C. E. LENZ July 4. 1967 y 3,329,895 DIGITAL PHASE COMPARATOR CAPABLE OF INDICATING GREATER THAN 560 DEGREE PHASE DIFFERENCES 8 Sheets-Sheet 'l Filed July 2, 1964 IN VEN TOR. CHARLES E LENZ um .0E

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AGENT July 4, 1967 Q E, LENZ 3,329,895

DIGITAL PHASE COMPARATOR CAPABLE OF INDICATING GREATER THAN 560 DEGREE PHASE DIFFERENCES Filed July 2, 1964 8 Sheets-Sheet 8 AGENT United States Patent O 3,329,895 DIGITAL PHASE COMPARATOR CAPABLE OF IN- DICATING GREATER THAN 360 DEGREE PHASE DIFFERENCES Charles E. Lenz, Fullerton, Calif., assigner to North American Aviation, Inc. Filed July 2, 1964, Ser. No. 379,997 Claims. (Cl. 324-83) This invention relates to a phase comparator and more specifically to a digital phase comparator having an output which varies as a function of the difference in phase between two periodic input functions.

One application of a phase comparator is demodulation of a phase-modulated signal by comparison of its phase with that of a carrier of iixed frequency. A common method of performing such demodulation is with a phase detector incorporating an inductance-capacitance circuit tuned to the fixed carried frequency. In such a state-ofthe-art phase detector, the output voltage corresponding to a given phase shift will vary if the resonant frequency -of the tuned circuit used drifts. Such drift may result from such cases as environmental variation and component aging. In addition, a conventional phase detector has a monotonically varying output only for phase angles within a range of i90 degrees. Beyond this range, the output of a conventional phase detector decreases as the absolute value of the phase shift increases. Further, the linearity of such a detector becomes progressively poorer as the phase difference departs from the value yielding zero output voltage. A further characteristic of a conventional detector is that it must be tuned to the reference frequency. Consequently, any variation -of the reference frequency will cause a bias to appear in the phase-detector output.

Accordingly, an object of the present invention is to provide a phase detector wherein the output for a given phase difference remains constant.

Another object of the invention is the provision of a phase detector which will provide a monotonically varying output over a range of phase angles exceeding 360 in absolute value. Y

Still another object of the invention is to provide a digital phase detector which operates with a linearity independent of the phase difference measured.

A feature of the present invention includes a phase comparator for measuring the phase difference between a irst and a second periodically varying signals including a digital counter which counts the cycles of the first signal in one direction and counts the cycles of the second signal in the opposite direction. The counter is then employed to give an output signal which varies as a function of the difference in phase of the two signals.

These Iand other objects, features and advantages of the present invention will become apparent from the following detailed description taken together with the accompanying drawing in which:

FIG. l illustrates a schematic diagram in block form of a phase comparator embodying the invention;

FIGS. 2(a)-2(f) illustrate waveforms and curves useful in explaining the invention;

FIG. 3 illustrates a schematic diagram in block form of the digital step detector illustrated in FIG. 1;

FIGS. 4(a)-4(l) illustrate waveforms useful in explaining the invention;

FIG. 5 illustrates a step counter which can be employed in the comparator illustrated in FIG. 1;

FIG. 6 illustrates a graph useful in explaining the invention;

FIG. 7 illustrates another step counter which can be employed in the comparator illustrated in FIG. 1;

3,329,895 Patented July 4, 1967 ICC FIG. 8 illustrates a digital to analog converter which can be used in the comparator illustrated in FIG. 1;

FIGS. 9(a)9(f) illustrate waveforms useful in explaining the invention; and

FIGS. 10(a)10(f) illustrate additional waveforms useful in explaining the invention.

A block diagram of the digital phase comparator embodying the invention is shown in FIG. l. The input signals e, and eo are commonly sinusoidal or square Waves and of the same frequency in the steady state. These two voltages need not, however, have the same waveforms. A primary clock signal C1 having a repetition rate harmonically related to the steady-state frequency of e, and e0' is employed. The secondary clock signal C2 is of the same repetition rate as C1, but is displaced electrical degrees from Cl at the clock frequency as shown in FIGS. 4(11) and (b). The quantized analog output voltageis directly proportional to the phase displacement of input e1 relative to input e2 over a specified range about zero phase displacement.

The digital phase comparator is comprised of the basic components listed below, along with a description of t-he functions of each:

Digital step detector The purpose of the step detector 10 is to emit an upcount pulse to the reversible step counter in response to each positive step of input e, and to emit a down-count pulse to that counter in response to each negative step of input eo. When either input signal, or both input signals, are sinusoidal, positive and negative slope zero crossings are interpreted as positive and negative steps, respectively. More specifically, when e, has a negative t-o positive zero crossing, circled in FIG. 2(b), an up-count pulse will be emitted from step detector 10. When a positive to negative zero crossing occurs in eo, as circled in FIG. 2(d), a down-count pulse will be emitted from detector 10. In each case, the pulse emitted will be from clock train C1. Output pulses will be emitted as soon as possi-ble consistent with logic provisions necessary to assure that no truncated clock pulses will be sent to the reversible step counter. In cases where the instantaneous phase displacement would cause count-up and count-down pulses to be emitted simultaneously, both pulses are inhibited.

Reversible step counter The purpose of the reversible step counter 20 is to keep a continuous tally of the total number of positive e, steps which have occurred minus the total number of negative eo steps which have occurred. In counting down one from 000 (in the case of a three-bit counter to be used as an example), the counter will recycle to lll. Thus the most significant bit represents the sign and is 1 only for negative numbers. The magnitude of negative numbers is represented in ones complement form.

The initial condition of the step counter is established by a preset pulse Yb applied to all counter flip-flops. Each nip-flop is designed so that this pulse disables all other inputs which the nip-flop may receive during its duration. If the preset pulse sets the counter to zero, if

where qb, and po are the phase angles of e1 and eo, respectively, and if the preset pulse and an up-count pulse from the step detector terminate simultaneously, the digital phase comparator will be in proper operation. Other sets of initial conditions are also possi-ble, of course.

The capacity of the reversible step counter must be adequate to accommodate the entire range of phase displacement possible. Each count corresponds to 21r radians of phase displacement. The step counter may be designed to count discontinuously for cyclic representation of phase displacement.

Digital to analog converter The purpose of the digital-to-analog converter 30 is to produce an instantaneous output voltage proportional to the contents of the reversible step counter, but biased positively by a voltage one-half that corresponding to a single count. An example of a digital-to-analog converter operating with a three-bit step counter is shown in the table below.

OPERATION OF THREE-BIT DIGITAL-TO-ANALOG CONVE RTE R Equivalent Step-Count Coefficients Output Decimal Count Voltage (C010 (E6) 1n a2 211 au s o 1 1 2 o 1 o 5- Bit Weight More generally, if an m-bit error counter is used, where m l, then the step count may be written m-l k Cslakz ,ak 0, l The output EE from the digital-to-analog converter will then be where kp is a constant of dimension volts. Note that the most significant, or sign, bit is Weighted negatively. In the table above, kp=l volt.

Averaging element The purpose of the averaging element 40 is to smooth the output of the digital-to-analog converter by averaging over a period of time optimum in respect both to the accuracy with which the average is represented and to the time delay introduced. By smoothing the output of digital-to-analog converter 30 to obtain the average or mean value thereof as a function of time, a voltage is obtained which is directly proportional to the instantaneous phase diiference between e1 and e0. One circuit suitable in many cases is a resistance-capacitance network having the transfer function 1 GAM-N+1 where r is a time constant of dimension seconds.

Typical operation of the digital phase comparator is illustrated by the voltage and phase relations in FIGS. 2(a)-2(f). The primary clock train C1 appears in FIG. 2(51). The input signals e1 and eD shown in FIGS. 2(b) and 2(d), respectively, are both sinusoidal voltages in this case, having steady-state frequencies one-eighth of the clock rate. Each positive-slope zero crossing of e1 is converted to a positive step by the digital step detector 10, which then causes the reversible step counter 20 to count up one. Each negative-slope zero crossing of eo is similarly converted to a negative step by the digital step detector 10, which then causes the reversible step counter 20 to count down one in the manner previously described. Operation of the step counter and the corresponding output voltage Ee from the digital-to-analog converter are shown by FIG. 2(1). The .phase angles of e1 and e0, designated p1 and 150, respectively, are plotted in FIGS. 2(c) and 2(e). The initial average value of EE is shown to be O. However, an increase Iof 21r radians in 1whi1e rpo remains fixed causes a corresponding increase in the average value of EE. Subsequently, the phase angle qb@ is also shown in increase from O to 2 radians; at this time, the average value of EE returns to zero, corresponding to the zero difference in phase between e1 and e0. The waveforms shown are typical of a servomechanism utilizing the digital phase comparator as an error detector. In such a case, e1 `would correspond to the input command generated by a phase encoder, and eo would correspond to the voltage furnished by a phase-encoding transducer attached to the output shaft.

Operation of each of the basic components described in the preceding section will now be discussed in detail. Two types of reversible step counters will be considered: The rst type causes an average output voltage E: to be generated which is directly proportional to the phase difference p1-gto over the entire permissible range of this difference, while the second type causes an average output voltage Ee to be generated which is a piecewise linear function of 1-o when that difference is defined as a cyclic variable of period 21m, where n is a positive integer.

Step detector (l0) The logic diagram of the step detector 10 is shown in FIG. 3. Inputs e1 and eD may be either sine or square waves of equal steady-state frequencies to which the clock repetition rate is harmonically related. The purpose of the step detector is to emit an up-count pulse at X1 soon after each positive step or positive-slope zero crossing of e1 and to emit a down-count pulse at X6 soon after each negative step or negative-slope zero crossing of ED. Pulses appearing at X1 and X5 are selected from clock-train C1 by the step detector; however, if the phase relationship between e1 and eo is such as to cause pulses to be emitted simultaneously at X1 and X6, both such simultaneous pulses will be inhibited.

A more detailed description of the above components is provided below. The electrical condition of the triggers and flip-Hops will be described as true or false If the trigger or flip-flop is described as in a true condition, this means that the upper of the ytwo outputs is one and the lower output is zero Hence, the ipops F11, F12, lF13 and F14 are all illustrated in a true state in FIG. 3. If the trigger or flip-Hop is described as false, this means the upper output is zero and the lower output one.

The triggers T11 and T12 (FIG. 3) are of the type (such as Schmidt triggers) that if the input goes negative to positive the output will be switched to a true output or condition. Hence, the positive going zero crossings of 951, shown in FIG. 2(a) will switch T11 into a true state. If the input of triggers T11 and T12 goes from positive to negative, the output will be switched from a true to a false condition.

When operating from sinusoidal inputs, triggers T11 and T12 are adusted to provide true outputs if, and only if, the signs of their respective input voltages are positive. When operating from square-wave inputs, a voltage level is chosen which is the steady-state average value of e1 or eo, respectively. Triggers T11 and T12 are then adusted to assume true states if, and only if, the instantaneous values of their input voltages are greater than E1u and Eza, respectively.

Flip-flops F11, F12, F13 and F11 of the step detector 10 are clocked R-S storage iiip flops. If a one is at the R input and a zero at the S input, these flip flops Will be switched to or maintained in a false condition when the next clock pulse arrives at the ilip flop. If a zero is at the R input and a one at the S input, these flip flops will be switched to or maintained in a true condition when the next lcock pulse arrives at the flip-flop.

The OpS F21, F22, F23, F51: F52 and F53 III 5 and 7 are simple T flip flops which change state from either true to false or false to true when a clock pulse is applied to the input. In using these flip flops in the counters il-lustrated in FIGS. 5 and 7 either leading or trailing edge triggering can be employed. If leading edge triggering is employed an inherent delay (in changing states) of slightly more than the time width of the clock pulse is necessary in the flip flop. If trailing edge triggering is employed, this delay can be less than the clock pulse time width.

Returning now to FIG. 3, when trigger T11 changes state, ilip-op F11 will .assume the same state at the time of the next C2 pulse. When flip-flop F11 changes state, ip-iiop F12 will assume the same state at the time of the next C1 pulse. In normal operation, if, and only if, F11 is true and F12 is false at the time of a C1 pulse, will that C1 pulse be emitted at X1. This situation exists only for one-half clock period following the rst C2 pulse after T11 goes true. The logic arrangement shown makes it impossible for a truncated clock pulse to be emitted at X1 and possibly cause improper operation of the step counter, regardless 4of the time at which T11 goes true.

In a manner similar to that just described, trigger T12 and flip-flops F13 and F14 act in response to input signal e1, to provide down-count pulses at X6. A difference exists, however, in the relationship Ibetween trigger T12 and iiipflop F13. At the next C2 pulse after trigger T12 changes state, ip-op F13 assumes the complement of that state. Thus, the rst C1 pulse following the first C2 pulse after T12 goes true Will be emitted at X6.

Or gate G11 is provided to prevent pulses from being emitted simultaneously at X1 and X1 and thereby causing improper oper-ation of the step counter. Immediately prior to the impending emission of such simultaneous pulses upon occurrence of the next C1 pulse, both F11 and F13 will be true, and both F12 and F14 will be false, thereby providing no true input to orgate G11. This situation will exist under no condition other than that stated. Consequently, and-gates G12 and G13 will be inhibited for the next C1 pulse, and no pulse will be emitted at either X1 or X5.

The logic equations which govern the operation of the digital step detector are listed below. Typical logic level symbols employed in these equations are illustrated in FIG. 3. As shown in FIG. 3, 1F11 is to the S (or set) input to ip-op F11.TF11 is the clock input to F11 and 0F11 is the R (or reset) input to F11. Corresponding symbols are employed for the inputs of other stages where 1 indicates the S or set input, T the clock input and 0 the R or reset input. The upper output of each block is indicated by the block designator. That is, the upper output of ip-op F11 is indicated as F11 whereas the lower output (shown as zero in FIG. 3) is indicated as '1511. Similar symbols are employed below for the other stages. These output symbols are also employed in FIGS. 4(a)-4(Z).

1F11=T11l (sa) TFH-:C2 }Fhpiiop F11 input equations (5b) 0F 11:71-'11 (5C) 1F12'=F11 (6a) TF12=C1 Wbp-flop F12 input equations (6b) oFiz'r-nl (6c) 1F13'=T 12 (7a) TF13=C2 Flip-flop F13 1nput equatlons (7b) 0F13'=T 12 (7C) 1F14=F13 (8a) TF111=C1 iFlip-op F11 input equations (8b) 0F14=F13l (8c) G12`=X1=C1F11F12G11l (9) }Output equations G1a=i=cflsii5nl (10) G11'=F11F12F13F14 (11) 1,e1 0] (12a) T11: lTrigger T11 equations trago] (12b) 1,eo 0 (13a) T12: LTrigger T12 equations deogoj (13b) Relations 12 and 13 apply only when e1 and eo are sinusoidal. For square waves, the zeros shown may be replaced by the steady-state average value of the square wave.

Waveforms pertaining to the step detector 10 are shown in FIGS. 4(a)4(l). Both inputs e1 and eo were chosen to be sinusoidal for this example. In this particular case, the zero crossings of input e1 are shown synchronized with pulses of clock train C1, as might occur if e1 were supplied by an input-command generator in a phase-comparison type servomechanism. When e1 is so synchronized and eo is not, a phase tolerance corresponding to plus or `minus one-half clock period occurs in the accuracy with which represents the phase difference between e1 and eo. If both e1 and e0 are both unsynchronized, this tolerance becomes twice as great as the value stated. As previously discussed, either e1 or e0, or both, may be square waves if desired. In the example illustrated in FIGS. 4(a)-4(l), the p-ops F11 and F12 are shown as initially being false (see FIGS. 4(e) and (f)) whereas F13 and F11 are shown to be true initially. It will be understood, however, that the detector will adjust itself and the initial condition of these ip ops is immaterial.

Step counter The output from the step detector 10, X1 and X1, shown in FIGS. 4(g) and (I) is applied to a reversible step counter 20, shown in detail in FIG. 5. The reversible step counter 20 is binary weighted and functions to keep a continuous tally of the total number of positive e1 steps (or positiveslope zero crossings) which have occurred minus the total number of negative e1, steps (or negative-slope Zero crossings) which have occurred. Two types of step counters are of interest. The first type maintains a count which varies monotonically with the phase difference 1-0, While the second type maintains a count which varies cyclically with this phase difference. Examples 4of three-bit counters of each type will be given. In each of these counters, a negative number is indicated by a 1 in the most significant bit position, and negative numbers are represented in ones complement form.

Counter f or monotonically varying output E, with phase dz'erence The logic diagram of .a three-bit reversible step counter for monotonically varying output E, with phase difference 1 0 is shown in FIG. 5. Any desired number of counter stages may be employed, and the maximum range of phase variation possible before an error results is 2n1r electrical radians, where n is the number of counter stages employed. To achieve maximum linearity of the variation of average output E, with phase difference, a counter design where all stages changing state do so approximately simultaneously is desirable. This is particularly important when updown counting is occurring between O00 and 111, for example.

The counter shown in FIG. 5 meets the requirement just discussed for simultaneous changes of state by all stages. Two input lines are provided: one for up-count pulses at X1, and one for down-count pulses at X5. Simultaneous, or almost simultaneous, arrival of pulses on both lines is not permissible. As discussed above, gates G11, G12, and G13 prevents such occurrence.

General logic rules govern the operation of the reversible counter in FIG. are as follows:

(a) The state of the lowest-order stage F21 will change whenever an up-count or a down-count pulse arrives.

(b) When an up-count pulse X1 arrives, the state of any stage of order other than the lowest will change if, and only if, the state of every lower-order stage is true.

(c) When a down-count pulse X, arrives, the state of any stage of order other than the lowest will change if, and only if, the state of every lower-order stage is false.

As in other figures in the drawing, the semicircular blocks with a dot in the middle are and gates. Thus G22, G23, G25 and G25 are and gates. Also as in the other figure, the semicircular block with a plus sign are or gates. Thus, G21, G24 and G22 are or gates. As described above, the iiip ops F21, F22 and F23 are simple T bistable flip flops which switch states upon receiving a clock pulse. These flip flops should have some internal delay between receiving the clock pulse and changing states. As set forth above, the amount of delay required depends on whether the ip llop is triggered by the leading or trailing edge of the flip op.

F21 represgnts the least significant bit of the binary counter 20 with F23 being the most significant bit and F22 next most signicant bit. The outputs X5, X1, and X2 supply the count of the device to be converted to an appropriate voltage such as illustrated in FIG. 2(1). A preset input Y1, is employed to initially condition iiip flops F21, F22 and F23. Preferably the initial condition is 000 so that all the flip ops are false. When the initial state of the counter is 000 (that is when F21, F22 and F23 are false) and a down-count pulse arrives, the counter will assume the state 111 that is F21, F22 and F23 will be true). It follows that it is possible to interpret the most significant bit F23 as representing the sign of the number in the counter, with a 1 in this position indicating a negative number, and with the magnitude of negative numbers being represented by the ones complement.

If the counter 20 shown in FIG. 5 is used for a reversible counter having a large number of stages, it is evident that the and gates associated with the highest order states will have a very large number of inputs. In such a case, a logic design is possible which is similar to that shown but which limits the size of the and gates required at some expense in operating synchronism.

The logic equations governing operation of the reversible counter shown in FIG. 5 are as follows:

TF21=G21=X5+X1 (14) TF22=G24=G22+G23 Flip-flop input equations (or gate equations) TF23=G27=G25+G26 (16) G22=1i2Xr l (17) Ggazll'zlX )And Gate equations The symbols employed in these equations are similar to those for detector 10. By way of explanation, Equation 14 sets forth that the input to F21 is the same as the input and output of or gate G21 so that a pulse at either X,5 or X1 will switch F21. Equation 17 illustrates that there is no output from and gate 22 unless F21 is true and there is an up-count pulse from X1. Equation 18 illustrates there is no output from and gate 23 unless F21 is false and there is a down-count pulse from X5, etc. Thus, the outputs' of counter X0, X1 and X2 are fed to a digital to analog converter which is explained below.

An alternate reversible counter 50 is illustrated in FIG.

7. This counter will provide a cyclically varying output LT;

with phase difference. In this alternate counter F51 is the least significant bit, F55 is the most signicant bit and F52 is the next most significant bit. The counter 50 is in this fashion binary weighted. These ip ops are T type described above. G51, G54 and G52 are or gates while G52, G53, G55, G55, G53 and G55 are and gates. A preset P is employed on F51, F52 and F53 to provide an initial condition.

The purpose of this cou nter 50 is to produce an average phase-difference voltage e, which varies in a quantized linear manner with the phase-difference e=10 for both positive and negative values of (pf, as in the case of the Counter previously described, over a specified range of (pc. However, the counter to be described has the addi tional capability of producing a voltage E, which is a piecewise linear function of rpg such that where n is a positive integer determined by the design of the counter, and m is any positive or negative integer, or zero. If the phase comparator is to be used as the error detector in a phase-comparison type angular-positioning servomechanism, n may be chosen to equal the number of radians of electrical phase shift p furnished by the output transducer for each radian of output-shaft motion. With such an arrangement, the output shaft will return to the position to which it has been commanded even after a disturbance torque greater than the output-torque capacity of the servomechanisrn has caused the output shaft to rotate any number of revolutions.

To achieve the above result, a step counter of sufficient capacity is gated to recycle in such a manner that the total number of counter states is where p has the meaning stated in the preceding paragraph. As an example, let 11:4. A three-bit counter with eight possible states is then chosen to permit Relation (24) to be satisfied. The number of possible counter states is then reduced to tive, as Relation (24) requires for this value yof p, by appropriate gating. To avoid any undesirable effects which an unstable null between adjacent stable nulls might produce, two different sequences are chosen for upward and downward counting, respectively. The sequences chosen for this example are shown in the table below.

The counting sequences shown in the table are cyclic, and the last number in each column represents the beginning of another cycle. The table may -be entered at any point. Any number of counts in either direction may result from an excessive disturbance torque.

COUNTING SEQUENCES OF THE THREE- BIT REVERSIBLE STEP COUNTER FOR CYCLICALLY VARYING OUTPUT C4 WITH PHASE DIFFERENCE be Upward Counting Downward Countingr FIG. 6 plots step count and the corresponding output voltage against the phase difference (pe. The numbers between which the reversible step counter will count for various value of phase difference (p, are shown in FIG. 6. In this figure, the horizontal axis is cyclic, so that proceeding beyond the scale in either direction results in entry at the `opposite end of the scale. To determine the average output voltage E, which corresponds to a given value of (ps, reference should be made to the linear-operation curve, shown as a light dotted line; the limitingoperation curve shown as a heavy dotted line will be dis- 9 cussed later. It will be noted that the average output voltage EE does not change between the largest positive value and the largest negative Value when e=n1r, i.e., at a point equidistant from adjacent stable nulls. The `angle 1 at which transition occurs approaches mr more closely as n increases.

The Ilogic diagram of a three-bit reversible step counter for cyclically varying output as a function of p, in a piecewise-linear manner is shown in FIG. 7. This logic diagram is similar to that shown in FIG. 5, except for the addition of gates G52 and G59 to introduce additional carry pulses into ip-flop F53. Due to such a carry pulses, this counter counts upward from 010 to lll, rather than to 011. Similarly, it counts downwards from 110 t-o 001, rather than to lOl. Otherwise, the counter counts normally, with the most significant bit representing the sign and with the amplitude of negative numbers represented in ones complement form. A negative sign is represented by a l.

The logic equations governing operation of the reversible step counter shown in FIG. 7 are as follows:

The symbols above are similar to those employed above for counter 20.

The output of the cyclically varying counter 50 is labeled as X2, X1, and X in FIG. 7. The flip-flops F51, F52 and F53 have presets for P to set the flip il-op in the preferred initial condition such as 000 discussed above. By so doing, the most significant bit gives the sign as described above.

Digital-to-analog converter The purpose of the digital-to-analog converter 30 is to produce an instantaneous output voltage EE corresponding to the instantaneous count CS in the step counter. The logic diagram for a digital-to-analog converter is shown in FIG. 8. The digital to analog converter 30 having inputs Y0, Y1 and Y2. X0 of co-center is shown in FIG. 8. The output 30 or 50 is connected to Y0, X1 is connected to Y1 and X2 is connected to Y2. When any of the outputs X0, X1 or X2 are one the corresponding transistor switch S0, S1, or S2, respectively, connects a voltage source E0, E1 or E2, respectively, to the input of an analog adder shown in block form. When any output X0, X1 or X2 is zero, this input is grounded. In practice, other means may also be used to obtain EE, such as switching resistance networks.

Two modes of operation will be discussed. In the rst mode, the instantaneous output voltage Ee varies linearly with the instantaneous step count Cs over the entire operating range of the step counter. The second mode is similar, except that the absolute value of li".E is limited to a magnitude no higher than some value [Eel maximum determined by the design of the phase comparator. These two modes of operation will be discussed separately.

Linear conversion (shown in light dotted Zine in FIG. 6)

The linear converter supplies an instantaneous output voltage in accordance with Formula 3, in column 3. For a three-bit digital-to-analog converter, the correspondence between step count and output voltage has already been 10 shown in the table in column 3 with the constant kp=1 volt.

To implement this table, it is only necessary to connect the outputs of the step counter shown in either FIG. 5 or FIG. 7 to the inputs of the digital-to-analog converter in FIG. 8 in sucha manner that where Yq are inputs of 30 X.,l or outputs of counter 20 or 50. This relation is the logic equation for linear conversion. Reference voltages are assigned tthe values shown in FIG. 8, viz.,

Eb=1/2 volt (38) E0=l volt (39) E1=2 volts (40) Connected in this manner, a three-bit step counter and digital-to-analog converter yield eight discrete voltage levels. A dilerent number lof levels can be obtained by varying the number of bits. The average voltage output e, obtained from the step counter in FIG. 7 operating in this mode with the digital-to-analog converter in FIG. 8 is plotted as the piecewise-linear-operation curve shown in light dotted lines in FIG. 6 as a function of phase difference of.

Limited conversion (shown in heavy dotted lines in FIG. 6)

In digital-to-analog conversion with limiting, a maximum value is established beyond which the absolute value of e, cannot rise. An example of such operation is shown by FIG. 6, where [alg/2 von (42) regardless of the value of the phase difference Such operation can be obtained with limiting at any desired level by placing a suitable network of logic gates between the outputs Xq of the step counter (either that in FIG. 5 or that in FIG. 7, for example) and the inputs Yr of the digital-to-analog converter. However, when the output voltage EE is to assume only two values as shown in FIG. 6, a particularly simple method of limiting exists. To implement the type of operation shown in FIG. 6, it is merely necessary to connect the output of the step counter 20 or 50 to the input of the converter in FIG. 8 so that Thus the output voltage EE is controlled by only the sign of the step count. The voltage sources E0 and E1 and `the switches S0 and S1 are not required in this case.

The output voltage EE is applied to averaging element 40 which smoothes the abruptly varying output of converter 30 to provide a voltage which varies continuously as a function of the instantaneous phase difference between e1 and eo. The manner in which this is accomplished will be more specifically described with reference to FIGS. 9(a)9(f) and FIGS. 10(a)l0(;f). In FIGS. 9(a)-9(f), it will be assumed that e1 and eo are equal in frequency but out of phase. In FIGS l0(a)-10(f) it will be assumed that there is a constant frequency diierence between e1 and e0 which will result in a constantly increasing phase diiference. Furthermore, in FIGS. 10(a) 10( f) it will be assumed that a step counter as is shown in FIG. 5 is used which maintains a count which varies monotonically with the phase difference p1-1%.

Referring now to the case where e1 and e0 are equal in frequency but 90 out of phase, the two input signals are shown in FIGS. 9(a) and 9(b). Each positive-slope zero lll crossing of e1, indicated by a circle in FIG. 9(0), is converted to a positive pulse by digital step detector 10 as shown in FIG. 9(0). Each negative-slope zero crossing of en, indicated by a circle in FIG. 9(b), is converted to a positive pulse by digital step detector 10 as shown in FIG. 9(d). The two trains of -pulses are then applied to reversible step counter 20 which is caused to add one count upon the application of a pulse at its up count input and subtract one count upon the application of a pulse at its down count input. The resultant digital signal from counter 20 is applied to digital-to-analog converter 30 which converts this signal to an analog voltage which varies between discrete voltage levels, as described previously, and which carries simultaneously with the change in the output of counter 20, i.e. upon the occurrence of an up count pulse or a down count pulse from detector 10. This operation is shown in FIG. 9(e). As can be seen from FIG. 9(e), and assuming that the phase of e, remains constant and only the phase of eo varies the position of edges 11-17 of waveform 18 follows the position of down count pulses 21-27 which indicate the negativeslope zero crossing of e0. If e and e1 are in phase, edges 11-17 of waveform 18 will be exactly half way between edges 31-38, the positions of which remain constant if el is constant, and the average or mean value of waveform 18 would be zero. However, since e, and e0 are 90 out of phase, in the example shown, the edges 11-17 are shifted with respect to edges 31-38 and the average or mean value of waveform 18 assumes a value which is greater than zero. This value is directly proportional to the position of edges 11-17 which, in turn, is directly proportional to the phase shift between el, and el. As a result, the output of averaging element 40, shown in FIG. 9(1), reaches a steady state value which indicates the 90 phase shift between e, and e0. In this manner, the output of averaging element 40 will indicate any incremental phase shift between e, and eo to any desired accuracy depending only on the frequency Iof the clock pulse input.

Referring now to the case where there is a constant frequency difference lbetween e1 and en, the two input signals are shown in FIGS. (11) and 10(1)). In the same manner as described with reference to FIGS. 9(a)9(f), two trains of pulses are derived, as shown in FIGS. 10(c) and l0(d), and applied to counter 20, which, in turn, controls the operation of digital to analog converter 30, the output of which is shown in FIG. 10(e). As can be readily seen from an inspection of FIGS. 10(6) to l0(e), the slightly greater frequency of e0 as compared with el causes the converter output to gradually assume a greater and greater negative value. The average or mean value of the converter 30 output, as shown in FIG. 10(1), will also increase gradually and at a rate which is directly proportional to the frequency difference between e, and e0. As a result, the value of EE at any given time is equal to the instantaneous phase shift between e, and eo.

Although only a preferred embodiment of the present invention has been described herein, it is not intended that the invention -be restricted thereto, but that it be limited only by the true spirit and scope of the appended claims.

I claim:

1. A phase comparator for producing an output signal representative of the instantaneous phase difference between a first and a second periodically varying signal comprising:

rneans responsive to a predetermined point in each cycle of said first signal for producing a third signal; means responsive to a predetermined point in each cycle `of said second signal for producing a fourth signal; means responsive to said third signal and said fourth signal for -producing a fifth signal, the amplitude of said fifth signal being capable of variation between at least three discrete levels, the amplitude of said fifth signal increasing to the next higher level upon the occurrence of said third signal and decreasing to the next lower level upon the occurrence of said fourth signal; and

means responsive to the mean value of said fifth signal for providing said output signal as a function thereof.

2. The phase comparator of claim 1 `further comprismg:

means for preventing application of said third and fourth signals to said means for producing a fifth signal when said third and fourth signals occur simultaneously.

3. The phase comparator of claim 1 wherein said means for providing said output signal comprises:

an averaging element for smoothing said voltage to provide a continuous signal indicative of Said phase difference.

d. A phase comparator for producing an output signal representative of the instantaneous phase difference between a first and a second periodically varying signal comprising:

means responsive to a predetermined point in each cycle of said first signal for producing a pulse so as to form a first pulse train;

means responsive to a predetermined point in each cycle of said second signal for producing a pulse so as to form a second pulse train;

means responsive to said first and second pulse trains for producing a third signal, the amplitude of said third signal being capable of variation between at least three discrete levels, the amplitude of said third signal increasing to the next higher level upon the occurrence of a pulse from said first pulse train and decreasing to the next lower level upon the occurrence of a pulse from said second pulse train; and

means responsive to the mean value 0f said third signal for providing said output signal as a function thereof.

5. The phase comparator of claim 4 further comprising:

means for preventing application of said first and second pulse trains to said means for producing a third signal when a pulse in said first pulse train and a pulse in said second pulse train occur simultaneously.

6. The phase comparator of claim 4 wherein said means for producing a third signal comprises:

a reversible counter having an up-count input responsive to said first pulse train and a down-count input respon-sive to said second pulse train; and

a digital-to-analog converter coupled to said counter for producing said third signal which varies as a function of the count in said counter.

7. The phase comparator of claim 6 wherein said reversible counter comprises:

a plurality of stages for providing a multiple-bit digital signal representing the instantaneous count in said counter and wherein the most significant bit of said digital signal indicates the sign of said count.

8. The phase comparator of claim 6 further comprismeans to preset said counter to zero.

9. The phase comparator of claim 6 wherein said digital-to-analog converter comprises:

a plurality of voltage sources;

switch means coupled to said plurality of voltage sources yand responsive to said count in said counter for selecting individual ones of said voltage sources to produce a composite voltage which varies between a plurality of discrete voltage levels, said switch means operative to increase said composite voltage when said count increases and decrease said composite voltage when said count decreases.

1-0. The phase comparator of claim 9 wherein said means for providing said output signal comprises:

an averaging element for smoothing said composite voltage to provide a ycontinuous signal indicative of lsaid phase difference.

References Cited UNITED STATES PATENTS Ball.

Grisdale 324-83 Kohler.

Moulton et a1. 324-79 RUDOLPH V. ROLINEC, Primary Examiner.

WALTER L. CARLSON, Examiner.

P. F. WILLE, Assistant Examiner. 

1. A PHASE COMPARATOR FOR PRODUCING AN OUTPUT SIGNAL REPRESENTATIVE OF THE INSTANTANEOUS PHASE DIFFERENCE BETWEEN A FIRST AND A SECOND PERIODICALLY VARYING SIGNAL COMPRISING: MEANS RESPONSIVE TO A PREDETERMINED POINT IN EACH CYCLE OF SAID FIRST SIGNAL FOR PRODUCING A THIRD SIGNAL; MEANS RESPONSIVE TO A PREDETERMINED POINT IN EACH CYCLE OF SAID SECOND SIGNAL FOR PRODUCING A FOURTH SIGNAL; MEANS RESPONSIVE TO SAID THIRD SIGNAL AND SAID FOURTH SIGNAL FOR PRODUCING A FIFTH SIGNAL, THE AMPLITUDE OF SAID FIFTH SIGNAL BEING CAPABLE OF VARIATION BETWEEN AT LEAST THREE DISCRETE LEVELS, THE AMPLITUDE OF SAID FIFTH SIGNAL INCREASING TO THE NEXT HIGHER LEVEL UPON THE OCCURENCE OF SAID THIRD SIGNAL AND DECREASING TO THE NEXT LOWER LEVEL UPON THE OCCURENCE OF SAID FOURTH SIGNAL; AND MEANS RESPONSIVE TO THE MEAN VALUE OF SAID FIFTH SIGNAL FOR PROVIDING SAID OUTPUT SIGNAL AS A FUNCTION THEREOF. 